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features ? single 2.7v - 3.6v supply serial peripheral interface (spi) compatible ? supports spi modes 0 and 3 70 mhz maximum clock frequency flexible, uniform erase architecture ? 4-kbyte blocks ? 32-kbyte blocks ? 64-kbyte blocks ? full chip erase optimized physical sectoring for code shadowing and code + data storage applications ? one 32-kbyte top boot sector ? two 8-kbyte sectors ? one 16-kbyte sector ? fifteen 64-kbyte sectors individual sector protection for program/erase protection hardware controlled locking of protected sectors flexible programming options ? byte/page program (1 to 256 bytes) ? sequential program mode capability jedec standard manufacturer and device id read methodology low power dissipation ? 7 ma active read current (typical) ? 11 a deep power-down current (typical) endurance: 100,000 program/erase cycles data retention: 20 years complies with full industrial temperature range industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150-mil and 200-mil wide) 1. description the at26df081a is a serial interface fl ash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from flash memory into embedded or external ram for execution. the flexible erase architecture of the at26df081a, with its erase granularity as small as 4 kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. the physical sectoring and the erase block sizes of the at26df081a have been opti- mized to meet the needs of today?s code and data storage applications. by optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. because certai n code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. this increased memory space efficiency allows addi- tional code routines and data storage segments to be added while still maintaining the same overall device density. 8-megabit 2.7-volt only serial firmware dataflash ? memory at26df081a preliminary 3600a?dflash?11/05
2 3600a?dflash?11/05 at26df081a [preliminary] the at26df081a also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. by providing the ability to individually pro- tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applica- tions where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. specifically designed for use in 3-volt system s, the at26df081a supports read, program, and erase operations with a supply voltage range of 2.7v to 3.6v. no separate voltage is required for programming and erasing. 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. output wp write protect: the wp pin controls the hardware locking feature of the device. please refer to section ?protection commands and features? on page 14 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. please refer to section ?hold? on page 26 for additional details on the hold operation. the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. power
3 3600a?dflash?11/05 at26df081a [preliminary] 3. block diagram 4. memory array to provide the greatest flexibility, the memory array of the at26df081a can be erased in four levels of granularity including a full chip erase. in addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations. the sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. the figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the breakdown of each physical sector. figure 2-1. 8-soic top view 1 2 3 4 8 7 6 5 c s s o wp gnd vcc hold s ck s i fla s h memory array y- g at i n g c s s ck s o s i y-decoder addre ss latch x-decoder i/o buffer s and latche s control and protection logic s ram data buffer wp interface control and logic
4 3600a?dflash?11/05 at26df081a [preliminary] figure 4-1. memory architecture diagram internal s ectorin g fo r 64kb 3 2kb 4kb 1-256 byte s ector protection block era s e block era s e block era s epa g e pro g ram function (d 8 h command) (52h command) (20h command) (02h command) 4kb 0fffffh ? 0ff000h 256 byte s 0fffffh ? 0fff00h 4kb 0fefffh ? 0fe000h 256 byte s 0ffeffh ? 0ffe00h 4kb 0fdfffh ? 0fd000h 256 byte s 0ffdffh ? 0ffd00h 4kb 0fcfffh ? 0fc000h 256 byte s 0ffcffh ? 0ffc00h 4kb 0fbfffh ? 0fb000h 256 byte s 0ffbffh ? 0ffb00h 4kb 0fafffh ? 0fa000h 256 byte s 0ffaffh ? 0ffa00h 4kb 0f9fffh ? 0f9000h 256 byte s 0ff9ffh ? 0ff900h 4kb 0f 8 fffh ? 0f 8 000h 256 byte s 0ff 8 ffh ? 0ff 8 00h 4kb 0f7fffh ? 0f7000h 256 byte s 0ff7ffh ? 0ff700h 4kb 0f6fffh ? 0f6000h 256 byte s 0ff6ffh ? 0ff600h 4kb 0f5fffh ? 0f5000h 256 byte s 0ff5ffh ? 0ff500h 4kb 0f4fffh ? 0f4000h 256 byte s 0ff4ffh ? 0ff400h 4kb 0f 3 fffh ? 0f 3 000h 256 byte s 0ff 3 ffh ? 0ff 3 00h 4kb 0f2fffh ? 0f2000h 256 byte s 0ff2ffh ? 0ff200h 4kb 0f1fffh ? 0f1000h 256 byte s 0ff1ffh ? 0ff100h 4kb 0f0fffh ? 0f0000h 256 byte s 0ff0ffh ? 0ff000h 4kb 0effffh ? 0ef000h 256 byte s 0fefffh ? 0fef00h 4kb 0eefffh ? 0ee000h 256 byte s 0feeffh ? 0fee00h 4kb 0edfffh ? 0ed000h 256 byte s 0fedffh ? 0fed00h 4kb 0ecfffh ? 0ec000h 256 byte s 0fecffh ? 0fec00h 4kb 0ebfffh ? 0eb000h 256 byte s 0febffh ? 0feb00h 4kb 0eafffh ? 0ea000h 256 byte s 0feaffh ? 0fea00h 4kb 0e9fffh ? 0e9000h 256 byte s 0fe9ffh ? 0fe900h 4kb 0e 8 fffh ? 0e 8 000h 256 byte s 0fe 8 ffh ? 0fe 8 00h 4kb 0e7fffh ? 0e7000h 4kb 0e6fffh ? 0e6000h 4kb 0e5fffh ? 0e5000h 4kb 0e4fffh ? 0e4000h 256 byte s 0017ffh ? 001700h 4kb 0e 3 fffh ? 0e 3 000h 256 byte s 0016ffh ? 001600h 4kb 0e2fffh ? 0e2000h 256 byte s 0015ffh ? 001500h 4kb 0e1fffh ? 0e1000h 256 byte s 0014ffh ? 001400h 4kb 0e0fffh ? 0e0000h 256 byte s 001 3 ffh ? 001 3 00h 256 byte s 0012ffh ? 001200h 256 byte s 0011ffh ? 001100h 256 byte s 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 byte s 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 byte s 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 byte s 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 byte s 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 byte s 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 byte s 000affh ? 000a00h 4kb 009fffh ? 009000h 256 byte s 0009ffh ? 000900h 4kb 00 8 fffh ? 00 8 000h 256 byte s 000 8 ffh ? 000 8 00h 4kb 007fffh ? 007000h 256 byte s 0007ffh ? 000700h 4kb 006fffh ? 006000h 256 byte s 0006ffh ? 000600h 4kb 005fffh ? 005000h 256 byte s 0005ffh ? 000500h 4kb 004fffh ? 004000h 256 byte s 0004ffh ? 000400h 4kb 00 3 fffh ? 00 3 000h 256 byte s 000 3 ffh ? 000 3 00h 4kb 002fffh ? 002000h 256 byte s 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 byte s 0001ffh ? 000100h 4kb 000fffh ? 000000h 256 byte s 0000ffh ? 000000h 64kb block era s e detail pa g e pro g ram detail pa g e addre ss block addre ss 3 2kb 3 2kb 64kb ( s ector 0) ran g e ran g e 3 2kb 3 2kb 3 2kb ( s ector 1 8 ) 8 kb ( s ector 17) 8 kb ( s ector 16) 16kb ( s ector 15) 64kb 3 2kb 3 2kb 64kb ( s ector 14) 64kb
5 3600a?dflash?11/05 at26df081a [preliminary] 5. device operation the at26df081a is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the spi master. the spi master communicates with the at26df081a via the spi bus which is comprised of four signal lines: chip select (cs ), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at26df081a supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 6. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin has been asserted, the spi master must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the spi master. all opcode, address, and data bytes are transferred with the most significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the at26df081a will be ignored by the device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation (cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address information is sent to the device, then no oper- ation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of th ree bytes of information to be sent, representing address bits a23 - a0. since the upper address limit of the at26df081a memory array is 0fffffh, address bits a23 - a20 are always ignored by the device. sck cs si so msb lsb msb lsb
6 3600a?dflash?11/05 at26df081a [preliminary] note: 1. three address bytes are only required for the first operation to designate the address to start programming at. afterwar ds, the internal address counter automatically increments, so subsequent sequential program mode operations only require clocking in of the opcode and the data byte until the sequential program mode has been exited. table 6-1. command listing command opcode address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 3 1 1+ read array (low frequency) 03h 0000 0011 3 0 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 3 0 0 block erase (32 kbytes) 52h 0101 0010 3 0 0 block erase (64 kbytes) d8h 1101 1000 3 0 0 chip erase 60h 0110 0000 0 0 0 c7h 1100 0111 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 3 0 1+ sequential program mode adh 1010 1101 3, 0 (1) 01 afh 1010 1111 3, 0 (1) 01 protection commands write enable 06h 0000 0110 0 0 0 write disable 04h 0000 0100 0 0 0 protect sector 36h 0011 0110 3 0 0 unprotect sector 39h 0011 1001 3 0 0 read sector protection registers 3ch 0011 1100 3 0 1+ status register commands read status register 05h 0000 0101 0 0 1+ write status register 01h 0000 0001 0 0 1 miscellaneous commands read manufacturer and device id 9fh 1001 1111 0 0 1 to 4 deep power-down b9h 1011 1001 0 0 0 resume from deep power-down abh 1010 1011 0 0 0
7 3600a?dflash?11/05 at26df081a [preliminary] 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the sck signal once the initial starting address has been speci- fied. the device incorporates an internal address counter that automatically increments on every clock cycle. two opcodes, 0bh and 03h, can be used for the read array command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the device. the 0bh opcode can be used at any sck frequency up to the maximum specified by f sck . the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. if the 0bh opcode is used, then one don't care byte must also be clocked in after the three address bytes. after the three address bytes (and the one don't care byte if using opcode 0bh) have been clocked in, additional clock cycles will result in serial data being output on the so pin. the data is always output with the msb of a byte first. when the last byte (0fffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array ? 0bh opcode figure 7-2. read array ? 03h opcode sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 3 9 42 43 41 40 37 38 33 36 35 34 31 32 2 9 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 2 9 30 3 9 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance
8 3600a?dflash?11/05 at26df081a [preliminary] 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 14 command description) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23 - a0 does not fall on an even 256-byte page boundary (a7 - a0 are not all 0?s), then special circumstances regarding which memory locations will be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for exam- ple, if the starting address denoted by a23 - a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will be unaffected and will not change. in addition, if more than 256 bytes of data are s ent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and pro- gram it into the appropriate memory array locations based on the starting address specified by a23 - a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be altered. the program- ming of the data bytes is internally self-timed and should take place in a time of t pp . the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); ot herwise, the device will abort the operation and no data will be pro- grammed into the memory array. in addition, if the address specified by a23 - a0 points to a memory location within a sector that is in the protected state (see section ?protect sector? on page 15 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state.
9 3600a?dflash?11/05 at26df081a [preliminary] the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. the byte/page program mode is the default programming mode after the device powers-up or resumes from a device reset. figure 8-1. byte program figure 8-2. page program 8.2 sequential program mode the sequential program mode improves throughput over the byte/page program command when the byte/page program command is used to pr ogram single bytes only into consecutive address locations. for example, some systems may be designed to program only a single byte of information at a time and cannot utilize a buffered page program operation due to design restrictions. in such a case, the system would no rmally have to perform multiple byte program operations in order to program data into sequential memory locations. this approach can add considerable system overhead and spi bus traffic. the sequential programming mode helps reduce system overhead and bus traffic by incorporat- ing an internal address counter that keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for every byte to program. when using the sequential program mode, all address locations to be programmed must be in the erased state. before the sequential program mode can first be entered, the write enable command must have been previously issued to the device to set the wel bit of the status reg- ister to a logical ?1? state. sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 3 9 37 38 33 36 35 34 31 32 2 9 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 4 9 83 9 37 38 33 36 35 34 31 32 2 9 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
10 3600a?dflash?11/05 at26df081a [preliminary] to start the sequential program mode, the cs pin must first be asserted, and either an opcode of adh or afh must be clocked into the device. for the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. after the address bytes have been clocked in, the byte of data to be programmed can be sent to the device. deasserting the cs pin will start the internally self-timed program operation, and the byte of data will be programmed into the memory location specified by a23 - a0. after the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the cs pin, clocking in the adh or afh opcode, and then clocking in the next byte of data. when the cs pin is deasserted, the second byte of data will be programmed into the next sequential memory location. the proce ss would be repeated for any additional bytes. there is no need to reissue the write enable command once the sequential program mode has been entered. when the last desired byte has been programmed into the memory array, the sequential program mode operation can be terminated by reasserting the cs pin and sending the write disable command to the device to reset the wel bit in the status register back to the logical ?0? state. if more than one byte of data is ever clocked in during each program cycle, then only the last byte of data sent on the si pin will be stored in the internal latches . the programming of each byte is internally self-timed and should take place in a time of t bp . for each program cycle, a complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the byte of data will not be programmed into the memory array, and the wel bit in the status register will be reset back to the logical ?0? state. if the address initially specified by a23 - a0 points to a memory location within a sector that is in the protected state, then the sequential program mode command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the sta- tus register will also be reset back to the logical ?0? state. there is no address wrapping when using the sequential program mode. therefore, when the last byte (0fffffh) of the memory array has been programmed, the device will automatically exit the sequential program mode and reset the wel bit in the status register back to the logi- cal ?0? state. in addition, the sequential program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatic ally exit the sequential program mode and reset the wel bit in the status register. for example, if sector 1 was protected and sector 0 was currently being programmed, once the last byte of sector 0 was programmed, the sequen- tial program mode would automatically end. to continue programming with sector 2, the sequential program mode would have to be restarted by supplying the adh or afh opcode, the three address bytes, and the first byte of sector 2 to program. while the device is programming a byte, the stat us register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled at the end of each program cycle rather than waiting the t bp time to determine if the byte has fin- ished programming before starting the next sequential program mode cycle. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register.
11 3600a?dflash?11/05 at26df081a [preliminary] figure 8-3. sequential program mode ? status register polling figure 8-4. sequential program mode ? waiting maximum byte program time 8.3 block erase a block of 4, 32, or 64 kbytes can be erased (all bits set to the logical ?1? state) in a single oper- ation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status reg- ister to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the device will erase the appropriate block. the erasing of the block is internally self- timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11 - a0 will be ignored by the device and their val ues can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14 - a0 will be ignored, and for a 64-kbyte erase, address bits a15 - a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. cs si so opcode a 23-16 a 15-8 a 7-0 05h data high-impedance opcode data 05h 04h opcode data 05h status register data status register data status register data seqeuntial program mode command first address to program status register read command write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) cs si so opcode a 23-16 a 15-8 a 7-0 data high-impedance opcode data 04h opcode data seqeuntial program mode command first address to program write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) t bp t bp t bp
12 3600a?dflash?11/05 at26df081a [preliminary] if the address specified by a23 - a0 points to a memory location within a sector that is in the pro- tected state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. in addition, with the larger block erase sizes of 32k and 64 kbytes, more than one physical sector may be erased (e.g. sectors 18 through 15) at one time. therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. if one of the physical sec- tors within the span is in the protected state, then the device will ignore the block erase command and will return to the idle state once the cs pin is deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase proper ly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-5. block erase sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 2 9 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
13 3600a?dflash?11/05 at26df081a [preliminary] 8.4 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been pre- viously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the chip erase command. there is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if any sector of the memory array is in the protected state, then the chip erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if a sector is in the protected state. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase proper ly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-6. chip erase sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance
14 3600a?dflash?11/05 at26df081a [preliminary] 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status regis- ter to a logical ?1? state. the wel bit must be set before a program, erase, protect sector, unprotect sector, or write status register command can be executed. this makes the issuance of these commands a two step process, ther eby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the command will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-1. write enable 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status reg- ister to the logical ?0? state. with the wel bit reset, all program, erase, protect sector, unprotect sector, and write status register commands will not be executed. the write disable command is also used to exit the sequential program mode. other conditions can also cause the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance
15 3600a?dflash?11/05 at26df081a [preliminary] figure 9-2. write disable 9.3 protect sector every physical sector of the device has a corresponding single-bit sector protection register that is used to control the software protection of a sector. upon device power-up or after a device reset, each sector protection register will default to the logical ?1? state indicating that all sectors are protected and cannot be programmed or erased. issuing the protect sector command to a particular sector address will set the corresponding sector protection register to the logical ?1? state. the following table outlines the two states of the sector protection registers. before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the protect sector command, the cs pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the sector protection register corresponding to the physical sector addressed by a23 - a0 will be set to the logical ?1? state, and the sector itself will then be protected from program and erase operations. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous protecting or unprotecting of sectors, the sector protection registers can themselves be locked from updates by using the sprl (sector protec- tion registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection regi sters are locked, then any attempts to issue the protect sector command will be ignored, and the device will reset the wel bit in the status reg- ister back to a logical ?0? and return to the idle state once the cs pin has been deasserted. sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance table 9-1. sector protection register values value sector protection status 0 sector is unprotected and can be programmed and erased. 1 sector is protected and cannot be programmed or erased. this is the default state.
16 3600a?dflash?11/05 at26df081a [preliminary] figure 9-3. protect sector 9.4 unprotect sector issuing the unprotect sector command to a particular sector address will reset the correspond- ing sector protection register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector pro- tection register that is used to control the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the unprotect sector command, the cs pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designat- ing any address within the sector to be unlocked must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the cs pin is deasserted, the sec- tor protection register corresponding to the sect or addressed by a23 - a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector pro- tection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the unprotect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-4. unprotect sector sck cs si so msb msb 23 1 0 00110110 67 5 41011 9 812 31 2 9 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance sck cs si so msb msb 23 1 0 00111001 67 5 41011 9 812 31 2 9 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
17 3600a?dflash?11/05 at26df081a [preliminary] 9.5 read sector protection registers the sector protection registers can be read to determine the current software protection status of each sector. reading the sector protection registers, however, will not determine the status of the wp pin. to read the sector protection register for a particular sector, the cs pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. after the last address byte has been clocked in, the device will begin outputting data on the so pin during every subse- quent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector protection registers, the software protection status (swp) bit in the status register can be read to determine if all, some, or none of the sectors are software protected (refer to the ?status register commands? on page 19 for more details). figure 9-5. read sector protection register table 9-2. read sector protection register ? output data output data sector protection register value 00h sector protection register value is 0 (sector is unprotected). ffh sector protection register value is 1 (sector is protected). sck cs si so msb msb 23 1 0 00111100 67 5 41011 9 812 3738 33 36 35 34 31 32 2 9 30 3 9 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte high-impedance
18 3600a?dflash?11/05 at26df081a [preliminary] 9.6 protected states and the write protect (wp ) pin the wp pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. instead, the wp pin, in conjunction with the sprl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the wp pin must be asserted and the sprl bit must be in the logical ?1? state. when hardware locking is active, the sector protection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the protect sector, unprotect sector, and write status register commands will be ignored. in order to modify the protection status of a sector, the wp pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state. if the wp pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle or reset the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to vcc, the sprl bit in the status register can still be set to a logical ?1? to lock the sector protection registers. this provides a software locking ability to prevent erroneous protect sector or unprotect sector com- mands from being processed. tables 9-3 and 9-4 detail the various protection and locking states of the device. note: 1. ?n? represents a sector number table 9-3. software protection wp sector protection register n(1) sector n(1) x (don't care) 0unprotected 1protected table 9-4. hardware and software locking wp sprl locking sprl sector protection registers 0 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands 01 hardware locked locked locked in current state. protect and unprotect sector commands will be ignored. 1 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands 11 software locked can be modified from 1 to 0 locked in current state. protect and unprotect sector commands will be ignored.
19 3600a?dflash?11/05 at26df081a [preliminary] 10. status register commands 10.1 read status register the status register can be read to determine the device's ready/busy status, as well as the sta- tus of many other functions such as hardware locking and software protection. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after the last bit of the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of the status register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the sck pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. bit 7 of the status register is the only bit that can be user modified. 2. r/w = readable and writable r = readable only table 10-1. status register format bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 sector protection registers are unlocked (default). 1 sector protection registers are locked. 6 spm sequential program mode status r 0 byte/page programming mode (default). 1 sequential programming mode entered. 5 epe erase/program error r 0 erase or program operation was successful (default). 1 erase or program error detected. 4 wpp write protect (wp ) pin status r 0wp is asserted. 1wp is deasserted. 3:2 swp software protection status r 00 all sectors are software unprotected. 01 some sectors are software protected. read sector protection registers. 10 reserved for future use. 11 all sectors are software protected (default). 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy/bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation.
20 3600a?dflash?11/05 at26df081a [preliminary] 10.1.1 sprl bit the sprl bit is used to control whether the sector protection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and can- not be modified with the protect sector and unprotect sector commands (the device will ignore these commands). any sectors that are presently protected will remain protected, and any sec- tors that are presently unprotected will remain unprotected. when the sprl bit is in the logical ?0? state, all sector protection registers are unlocked and can be modified (the protect sector and unprotect sector commands will be processed as nor- mal). the sprl bit defaults to the logical ?0? state after a power-up or a device reset. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sector protection regis- ters are unlocked) to a logical ?1? (sector protection registers are locked). in order to reset the sprl bit back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the sprl bit is the only bit of the status register than can be user modified via the write status register command. 10.1.2 spm bit the spm bit indicates whether the device is in the byte/page program mode or the sequential program mode. the default state after power-up or device reset is the byte/page program mode. 10.1.3 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or pro- gram operation aborts for any reason such as an attempt to erase or program a protected region or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 10.1.4 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 10.1.5 swp bits the swp bits provide feedback on the software protection status for the device. there are three possible combinations of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector command. if the swp bits indicate that some of the sectors have been protected, then the individual sector protection registers can be read with the read sector protection registers command to determine which sectors are in fact protected.
21 3600a?dflash?11/05 at26df081a [preliminary] 10.1.6 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any program, erase, protect sector, unprotect sector, or write status register commands. the wel bit defaults to the logical ?0? state after a device power-up or reset. in addition, the wel bit will be reset to the logical ?0? state automati- cally under the following conditions: write disable operation completes successfully write status register operation completes successfully or aborts protect sector operation completes successfully or aborts unprotect sector operation completes successfully or aborts byte/page program operation completes successfully or aborts sequential program mode reaches highest unprotected memory location sequential program mode reaches the end of the memory array sequential program mode aborts block erase operation completes successfully or aborts chip erase operation completes successfully or aborts hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, protect sector, unprotect sector, or write status register com- mand must have been clocked into the device. 10.1.7 rdy/bsy bit the rdy/bsy bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. to poll the rdy/bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 10-1. read status register sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 1 9 18 15 16 13 14 23 24 opcode msb msb dddddd d d d d msb ddddd d d d status register data status register data high-impedance
22 3600a?dflash?11/05 at26df081a [preliminary] 10.2 write status register the write status register command is used to modify the sprl bit of the status register. before the write status register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device. after the opcode has been clocked in, one byte of data comprised of the sprl bit value and seven don't care bits must be clocked in. any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status register will be modified, and the wel bit in the status register will be reset back to a logical ?0?. the complete one byte of data must be clocked into the device before the cs pin is deasserted; otherwise, the device will abort the operation, the state of the sprl bit will not change, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register command will be ignored, and the wel bit in the status register will be reset back to the logical ?0? state. in order to reset the sprl bit to a logical ?0?, the wp pin must be deasserted. figure 10-2. write status register sck cs si so msb 23 1 0 0000000 67 5 41011 9 81415 13 12 opcode msb 1dxxxxx x x status register in high-impedance
23 3600a?dflash?11/05 at26df081a [preliminary] 11. other commands and functions 11.1 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin out- putting the identification data on the so pin dur ing the subsequent clock cycles. the first byte that will be output will be the manufacturer id fo llowed by two bytes of device id information. the fourth byte output will be the extended device information string length, which will be 00h indicating that no extended device information follows. after the extended device information string length byte is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 11-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 45h 3 device id (part 2) 01h 4 extended device information string length 00h table 11-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 5 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for atmel) 00011111 device id (part 1) family code density code 45h family code: 010 (at26dfxxx series) density code: 00101 (8-mbit) 01000101 device id (part 2) mlc code product version code 01h mlc code: 000 (1-bit/cell technology) product version: 00001 (first major revision) 00000001
24 3600a?dflash?11/05 at26df081a [preliminary] figure 11-1. read manufacturer and device id 11.2 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consump- tion state called the deep power-down mode. when the device is in the deep power-down mode, all commands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle or a device reset. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. sck cs si so 6 0 9 fh 8 7 38 opcode 1fh 45h 01h 00h manufacturer id device id byte 1 device id byte 2 extended device information string length high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
25 3600a?dflash?11/05 at26df081a [preliminary] figure 11-2. deep power-down 11.3 resume from deep power-down in order exit the deep power-down mode and resume normal device operation, the resume from deep power-down command must be issued. the resume from deep power-down com- mand is the only command that the device will recognize while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power- down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 11-3. resume from deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
26 3600a?dflash?11/05 at26df081a [preliminary] 11.4 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won't be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the hold mode won't end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the wel bit in the status register back to the logical ?0? state. figure 11-4. hold mode sck cs hold hold hold hold
27 3600a?dflash?11/05 at26df081a [preliminary] 12. electrical specifications 12.1 absolute maximum ratings* temperature under bias ............................... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground .....................................-0.6v to +4.1v all output voltages with respect to ground .............................-0.6v to v cc + 0.5v 12.2 dc and ac operating range at26df081a operating temperature (case) ind. -40 c to 85 c v cc power supply 2.7v to 3.6v 12.3 dc characteristics symbol parameter condition min typ max units i sb standby current cs , wp , hold = v cc , all inputs at cmos levels 25 35 a i dpd deep power-down current cs , wp , hold = v cc , all inputs at cmos levels 11 15 a i cc1 active current, read operation f = 70 mhz; i out = 0 ma; cs = v il , v cc = max 12 16 ma f = 66 mhz; i out = 0 ma; cs = v il , v cc = max 11 15 f = 50 mhz; i out = 0 ma; cs = v il , v cc = max 10 14 f = 33 mhz; i out = 0 ma; cs = v il , v cc = max 812 f = 20 mhz; i out = 0 ma; cs = v il , v cc = max 710 i cc2 active current, program operation cs = v cc , v cc = max 12 18 ma i cc3 active current, erase operation cs = v cc , v cc = max 14 20 ma i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6 ma; v cc = min 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
28 3600a?dflash?11/05 at26df081a [preliminary] notes: 1. not 100% tested (value guaranteed by design and characterization). 2. 15 pf load at 70 mhz, 30 pf load at 66 mhz. 3. only applicable as a constraint for the write status register command when sprl = 1 12.4 ac characteristics symbol parameter min max units f sck serial clock (sck) frequency 70 mhz f rdlf sck frequency for read array (low frequency - 03h opcode) 33 mhz t sckh sck high time 6.4 ns t sckl sck low time 6.4 ns t sckr (1) sck rise time, peak-to-peak (slew rate) 0.1 v/ns t sckf (1) sck fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chip select high time 50 ns t csls chip select low setup time (relative to sck) 5 ns t cslh chip select low hold time (relative to sck) 5 ns t cshs chip select high setup time (relative to sck) 5 ns t cshh chip select high hold time (relative to sck) 5 ns t ds data in setup time 2 ns t dh data in hold time 3 ns t dis (1) output disable time 6 ns t v (2) output valid time 6ns t oh output hold time 0 ns t hls hold low setup time (relative to sck) 5 ns t hlh hold low hold time (relative to sck) 5 ns t hhs hold high setup time (relative to sck) 5 ns t hhh hold high hold time (relative to sck) 5 ns t hlqz (1) hold low to output high-z 6 ns t hhqx (1) hold high to output low-z 6 ns t wps (1)(3) write protect setup time 20 ns t wph (1)(3) write protect hold time 100 ns t secp (1) sector protect time (from chip select high) 20 ns t secup (1) sector unprotect time (from chip select high) 20 ns t edpd (1) chip select high to deep power-down 3 s t rdpd (1) chip select high to standby mode 3 s
29 3600a?dflash?11/05 at26df081a [preliminary] note: 1. not 100% tested (value guaranteed by design and characterization). 12.7 input test waveforms and measurement levels t r , t f < 2 ns (10% to 90%) 12.8 output test load 12.5 program and erase characteristics symbol parameter min typ max units t pp page program time (256 bytes) 1.5 3.0 ms t bp byte program time 6 s t blke block erase time 4 kbytes 0.05 0.2 sec 32 kbytes 0.35 0.6 64 kbytes 0.7 1.0 t chpe chip erase time 10 14 sec t wrsr (1) write status register time 200 ns 12.6 power-up conditions parameter min max units minimum v cc to chip select low time 50 s power-up device delay before program or erase allowed 10 ms power-on reset voltage 1.5 2.5 v ac driving level s ac mea s urement level 0.45v 1.5v 2.4v device under te s t 3 0 pf
30 3600a?dflash?11/05 at26df081a [preliminary] 13. waveforms figure 13-1. serial input timing figure 13-2. serial output timing figure 13-3. hold timing ? serial input c s s i s ck s o m s b high-impedance m s b l s b t c s l s t s ckh t s ckl t c s h s t c s hh t d s t dh t c s lh t c s h cs si sck so t v t sckh t sckl t dis t v t oh c s s i s ck s o t hhh t hl s t hlh t hh s hold high-impedance
31 3600a?dflash?11/05 at26df081a [preliminary] figure 13-4. hold timing ? serial output figure 13-5. wp timing for write status register command when sprl = 1 cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx wp si sck so 00 0 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode
32 3600a?dflash?11/05 at26df081a [preliminary] 14. ordering information 14.1 green package options (pb/halide-free/rohs compliant) f sck (mhz) ordering code package operation range 70 at26df081a-ssu 8s1 industrial (-40 c to 85 c) AT26DF081A-SU 8s2 package type 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.209? wide, plastic gull wing small outline package (eiaj soic)
33 3600a?dflash?11/05 at26df081a [preliminary] 15. packaging information 15.1 8s1 ? eiaj soic 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. note: 3 /17/05 8s 1 , 8 -le a d (0.150" wide body), pl as tic g u ll wing s m a ll o u tline (jedec s oic) 8s 1c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 the s e dr a wing s a re for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. ? ? e e 1 1 n n top view c c e1 e 1 end view a a b b l l a1 a 1 e e d d s ide view
34 3600a?dflash?11/05 at26df081a [preliminary] 15.2 8s2 ? eiaj soic 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8s 2 , 8 -le a d, 0.209" body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 10/7/0 3 8s 2 c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . it i s recommended th a t u pper a nd lower c a vitie s b e e qua l. if they a re different, the l a rger dimen s ion s h a ll b e reg a rded. 4. determine s the tr u e geometric po s ition. 5. v a l u e s b a nd c a pply to p b / s n s older pl a ted termin a l. the s t a nd a rd thickne ss of the s older l a yer s h a ll b e 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 5 c 0.15 0. 3 5 5 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2, 3 e 7.70 8 .26 l 0.51 0. 8 5 ? 0 8 e 1.27 b s c 4 end view s ide view e b a a1 d e n 1 c e1 ? l top view
35 3600a?dflash?11/05 at26df081a [preliminary] 16. revision history version no./release date history revision a ? november 2005 ? initial release
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